Semiconductor device and method
US12266541B2 · kind B2 · utility
0Cited by
21References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Jan 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes: forming a photoresist over a target layer; performing a plasma-enhanced deposition process, the plasma-enhanced deposition process etching sidewalls of the photoresist while depositing a spacer layer on the sidewalls of the photoresist; patterning the spacer layer to form spacers on the sidewalls of the photoresist; and etching the target layer using the spacers and the photoresist as a combined etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.