Method of forming semiconductor device having at least one via including concave portions on sidewall
US12266593B2 · kind B2 · utility
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20Claims
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Assignee
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Key dates
| Filing date | Aug 2, 2023 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.