Flash memory devices with thickened source/drain silicide
US12266702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Aug 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Structures for a memory device and methods of forming a structure for a memory device. The structure includes a first and second source/drain regions in a semiconductor substrate, a first gate stack on the semiconductor substrate, and a second gate stack on the semiconductor substrate adjacent to the first gate stack. The first and second gate stacks are positioned in a lateral direction between the first source/drain region and the second source/drain region. The first gate stack includes first and second gate electrodes, and the first gate electrode includes segments spaced apart along a longitudinal axis of the first gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.