Inventor · Singapore, SG

Young Way Teh

25Patents
8h-index
63Co-inventors
78Inventor score

Filing activity: Nov 27, 2000 → Jun 8, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7759206B2 Methods of forming semiconductor devices using embedded L-shape spacers Electricity 116 Expired
US7867835B2 Integrated circuit system for suppressing short channel effects Electricity 115 Active
US6406975B1 Method for fabricating an air gap shallow trench isolation (STI) structure Electricity 51 Expired
US6380106B1 Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures Electricity 34 Expired
US6649517B2 Copper metal structure for the reduction of intra-metal capacitance Electricity 19 Expired
US7297584B2 Methods of fabricating semiconductor devices having a dual stress liner Electricity 17 Expired
US7256084B2 Composite stress spacer Electricity 12 Expired
US7445978B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Electricity 11 Expired
US7785950B2 Dual stress memory technique method and related structure Electricity 7 Active
US6815823B2 Copper metal structure for the reduction of intra-metal capacitance Electricity 6 Expired
US8624329B2 Spacer-less low-K dielectric processes Electricity 5 Active
US7531401B2 Method for improved fabrication of a semiconductor using a stress proximity technique process Emerging Cross-Sectional Technologies 5 Active
US7883953B2 Method for transistor fabrication with optimized performance Electricity 4 Active
US7993997B2 Poly profile engineering to modulate spacer induced stress for device enhancement Electricity 3 Active
US7999325B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Electricity 3 Active
US7615427B2 Spacer-less low-k dielectric processes Electricity 3 Active
US7977185B2 Method and apparatus for post silicide spacer removal Electricity 3 Expired
US7307320B2 Differential mechanical stress-producing regions for integrated circuit field effect transistors Electricity 2 Expired
US8563394B2 Integrated circuit structure having substantially planar N-P step height and methods of forming Electricity 2 Active
US8853796B2 High-K metal gate device Electricity 0 Active
US8461009B2 Spacer and process to enhance the strain in the channel with stress liner Electricity 0 Active
US12266702B2 Flash memory devices with thickened source/drain silicide Electricity 0 Active
US8664717B2 Semiconductor device with an oversized local contact as a Faraday shield Electricity 0 Active
US8519445B2 Poly profile engineering to modulate spacer induced stress for device enhancement Electricity 0 Active
US8106462B2 Balancing NFET and PFET performance using straining layers Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.