3-dimensional NAND memory with reduced thermal budget
US12267999B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jul 13, 2020 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Nov 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
Methods of manufacture and memory cells manufactured according to the methods are described. The manufacture has a lower thermal budget and experiences less heating by including a blocking layer including MgO. The method of manufacture may include annealing following deposition of the MgO, with the annealing occurring at temperatures below 900° C. or below 800° C. The blocking layers may be a first blocking layer made of SiO2 and a second blocking layer made of MgO. The memory cells may have a CMOS Under Array (CuA) structure. The memory cells may be part of a three-dimensional NAND memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.