Integrated circuit with constrained metal line arrangement, method of using, and system for using
US12271678B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jul 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of making an integrated circuit includes dividing, in a first layer of an integrated circuit layout, a first arrangement of metal lines into a first set of metal lines and a second set of metal lines, wherein the first set of metal lines is between the second set of metal lines and a periphery of the integrated circuit layout, wherein the first arrangement of metal lines is configured to electrically connect to a plurality of contacts connected to a second layer of the integrated circuit layout after a manufacturing process. The method further includes adjusting a metal line perimeter of at least one metal line in the second set of metal lines to make a second arrangement of metal lines, wherein each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.