Performing selective copyback in memory devices
US12272412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Dec 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.