Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance

US12272741B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Man-Ho Kwan · Kowloon, CN
• Fu-Wei Yao · Hsinchu, TW
• Chun Lin Tsai · Baoshan, TW
• Jiun-Lei Jerry Yu · Dashulong, TW
• Ting-Fu Chang · Taipei, TW

Key dates

• Filing date: Aug 3, 2023
• Grant date: Apr 8, 2025
• Expiry date: Aug 3, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.