Computer system having a chip configured for memory attachment and routing
US12273268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | May 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory attachment and routing chip includes a single die having a set of external ports; at least one memory attachment interface comprising a memory controller to attach to external memory, and a fabric core in which routing logic is implemented. The routing logic can (i) receive a first packet of a first type from a first port of the set of ports, the first type of packet being a memory access packet with a memory address which lies in a range of memory addresses associated with the memory attachment and routing chip, detect the memory address and route the packet of the first type to the memory attachment interface. The routing logic can (ii) receive a second packet of a second type, the second type of packet being an inter-processor packet comprising a destination identifier identifying a processing chip external to the memory attachment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.