Selective mesh routing through non-adjacent nodes
US12273269B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/42
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.