Error correction for computational memory modules
US12277076B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 19, 2023 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks, formed on a common substrate. The computational memory system also includes at least one local error correction code (ECC) module configured for calculating an original ECC based on received data, at least one local ECC module associated with at least one of the processor subunits and/or at least one of the memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.