Page buffer circuits in three-dimensional memory devices
US12277993B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 23, 2024 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Jan 23, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.