Hybrid embedded packaging structure and manufacturing method thereof
US12278227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2022 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Aug 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92247
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.