Multi-channel devices and method with anti-punch through process
US12278276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.