Performing constant modulo arithmetic
US12282751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2022 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary logic circuit for determining y=x mod(2m−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.