Memory BIST circuit and method
US12283332B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 2022 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Mar 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.