Wafer bonding alignment
US12283568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2023 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Sep 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.