Shared well structure manufacturing method
US12288786B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 24, 2023 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Nov 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.