Semiconductor device with doped structure
US12288809B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 21, 2024 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Mar 21, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.