Scaled quantum circuits
US12290008B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/0912
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for forming respective groups of quantum circuit elements (QCEs) on respective crystalline surfaces of a crystalline dielectric (CD) layer are presented. Vias can be formed in the CD layer. Second QCEs can be formed on a second crystalline surface of the CD layer. A seal layer can be applied to the patterned second metallization layer that forms the second QCEs. A handle wafer can be bonded to the seal layer. The chip stack can be turned over to place a substrate at the top, and handle wafer at the bottom, of the chip stack. The substrate and a buried oxide layer can be removed to expose the first crystalline surface of the CD layer. First QCEs can be formed on the first crystalline surface of the CD layer. A portion of the first QCEs can be coupled or interconnected to a portion of the second QCEs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.