Multiple memory block erase operation
US12293080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2023 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Aug 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.