Neural network based mask synthesis for integrated circuits
US12293279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2020 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Nov 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system uses machine learning models, such as neural networks for generating mask design from a circuit design. The machine learning models have inputs and outputs which are localized to a small region of the circuit design. The machine learning model takes as input features describing the circuit design in the neighborhood of a location and generates an offset distance as output. The system uses the offset distance to generate features of the mask design, for example, main features or assist features corresponding to a circuit design polygon. The system may use the offset distance for target optimization by modifying the circuit design polygon to obtain a circuit design polygon that has improved manufacturability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.