Managing defective blocks during multi-plane programming operations in memory devices
US12293795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2022 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.