Directed self-assembly enabled subtractive metal patterning

US12293913B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Gurpreet Singh · Alwar, IN
• Richard E. Schenker · Portland, US
• Nityan NAIR · Portland, US
• Nafees Kabir · Portland, US
• Gauri Nabar · Hillsboro, US
• Eungnak Han · Portland, US
• Xuanxuan Chen · Heverlee, BE
• Tayseer Mahdi · Hillsboro, US
• Brandon Holybee · Portland, US
• Charles H. Wallace · Portland, US
• Paul A. Nyhus · Portland, US
• Manish Chandhok · Beaverton, US
• Florian Gstrein · Portland, US

Key dates

• Filing date: Dec 22, 2021
• Grant date: May 6, 2025
• Expiry date: Dec 23, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/53209
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.