Asymmetrical clock separation and stage delay optimization in single flux quantum logic
US12294369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2022 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Jul 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.