Memory controller and memory system performing wear-leveling
US12299323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.