Detecting and mitigating memory attacks
US12300304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40618
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. For example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. The memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and/or transitioning back to the counting mode. By selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.