Reconfigurable memory module designed to implement computing operations
US12300347B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | May 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present description concerns a memory module (100) adapted to implementing computing operations, the module comprising a plurality of elementary blocks (110) arranged in an array according to rows and columns, wherein: each elementary block (110) comprises a memory circuit (111) adapted to implementing computing operations, and a configurable transfer circuit (113); each configurable transfer circuit (113) is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit (120) is connected to an input-output port (123) of the module; and the internal control circuit (120) is configured to read at least one instruction signal from the input-output port (123) of the module and accordingly parameterize the configuration of the configurable transfer circuits (113), and define the size of the operand vectors of the computing operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.