Reducing internal node loading in combination circuits
US12300605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Nov 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.