Hybrid integrated circuit package
US12300621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | May 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5383
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are multi-layer substrates for integrated circuit packages and methods of making the same. The multi-layer substrate may comprise a plurality of lower layers, at least one core layer, a plurality of upper layers, and a side surface. A first connection and a second connection may extend through or on an uppermost layer of the plurality of upper layers. A trace may be embedded in or on one of the plurality of upper layers, the trace electrically connected to the first connection and the second connection. A first mounting pad and a second mounting pad may be positioned on the side surface and/or the uppermost layer of the plurality of upper layers and a blocking capacitor may be electrically connected to the first mounting pad and the second mounting pad with the second mounting pad electrically connected to the second connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.