Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal
US12301236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Nov 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.