Patent · US Active

Three-dimensional memory device with divided drain select gate lines and method for forming the same

US12302560B2 · kind B2 · utility

0Cited by
8References
20Claims
0Family size

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Inventors

Key dates

Filing dateJan 4, 2022
Grant dateMay 13, 2025
Priority date
Expiry dateNov 12, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/679

Abstract

A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.