Link down resilience
US12306719B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jul 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A link layer reliability (LLR) circuit of a communication device can receive an indication that a link down event has occurred on a bus link with a peer device. The LLR circuit can prevent the link down event from triggering a reset of configuration registers containing bus settings for the bus link. Once the bus link has been restored, the LLR circuit can send a retry request to the peer device indicating an expected sequence number associated with a transaction that the LLR circuit is expecting from the peer device. The LLR circuit may receive a retry acknowledgment from the peer device indicating receipt of the retry request for the transaction corresponding to the expected sequence number, and payload data for the transaction corresponding to the expected sequence number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.