Hardware acceleration for computing eigenpairs of a matrix

US12306902B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Tomasz J. Nowicki · Peekskill, US
• Oguzhan Murat Onen · Boston, US
• Tayfun Gokmen · Briarcliff Manor, US
• Vasileios Kalantzis · White Plains, US
• Chai Wah Wu · Poughquag, US
• Mark S. Squillante · Pound Ridge, US
• Malte Johannes Rasch · Chappaqua, US
• Wilfried E. Haensch · Somers, US
• Lior Horesh · North Salem, US

Key dates

• Filing date: Apr 30, 2021
• Grant date: May 20, 2025
• Expiry date: Feb 3, 2044

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/065
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.