Memory device programming technique for increased bits per cell
US12307090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2024 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Mar 21, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.