Managing power loss recovery using a dirty section write policy for an address mapping table in a memory sub-system
US12314177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2024 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Feb 15, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. Respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. It is determined that the total count for the address mapping table satisfies a threshold criterion. A first section of the plurality of sections with a highest section count is identified based on the respective section counts. The first section of the address mapping table is written to a non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.