Memory device and program operation thereof
US12315568B2 · kind B2 · utility
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1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2024 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jan 4, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.