Differential memory cell array structure for multi-time programming non-volatile memory
US12315569B2 · kind B2 · utility
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7Claims
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Key dates
| Filing date | Mar 10, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Sep 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.