Edge encapsulation for high voltage devices
US12315770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/293
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.