Semiconductor structure and manufacturing method thereof
US12315786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.