Skip level vias in metallization layers for integrated circuit devices

US12315794B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Adel A. Elsherbini · Chandler, US
• Mauro J. Kobrinsky · Portland, US
• Shawna M. Liff · Scottsdale, US
• Johanna M. Swan · Scottsdale, US
• Gerald Pasdast · San Jose, US
• Sathya Narasimman Tiagaraj · San Jose, US

Key dates

• Filing date: Dec 23, 2022
• Grant date: May 27, 2025
• Expiry date: Jul 16, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06544
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.