Methods of manufacturing a fan-out panel level semiconductor package
US12315822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2024 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jan 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.