Patent · US Active

Error processing and correction of adjacent 2-bit errors

US12316346B2 · kind B2 · utility

0Cited by

10References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jens Rosenbusch · Munich, DE
Klaus Oberlander · San Jose, US
Georg Duchrau · Preddöhl, DE
Michael Goessel · Roter Dudel, DE

Key dates

Filing date	Jul 20, 2023
Grant date	May 27, 2025
Priority date	—
Expiry date	Jul 25, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6575
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.