Three-dimensional memory device and fabrication method for enhanced reliability
US12317491B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 29, 2021 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Apr 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.