High electron mobility transistors having barrier liners and integration schemes

US12317562B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Ramsey Hazbun · Colchester, US
• Anthony K. Stamper · Williston, US
• Zhong-Xiang He · South Burlington, US
• Pernell Dongmo · South Burlington, US

Key dates

• Filing date: Nov 16, 2021
• Grant date: May 27, 2025
• Expiry date: Jul 17, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/478

Abstract

A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.