Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions

US12317585B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sairam Subramanian · Dallas, US
• Walid M. Hafez · Portland, US
• Hsu-Yu Chang · Hillsboro, US
• Chia-Hong Jan · Portland, US
• Tanuj Trivedi · Hillsboro, US

Key dates

• Filing date: Sep 18, 2020
• Grant date: May 27, 2025
• Expiry date: Aug 2, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0128

Abstract

Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.