Integrated circuit

US12317751B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Tai-Yen Peng · Hsinchu, TW
• Chien-Chung Huang · Tainan, TW
• Yu-Shu Chen
• Sin-Yi Yang · Taichung, TW
• Chen-Jung Wang · Hsinchu, TW
• Han-Ting Lin · Hsinchu, TW
• Chih-Yuan Ting · Taipei, TW
• Jyu-Horng Shieh · Hsinchu, TW
• Hui-Hsien Wei · Taoyuan, TW

Key dates

• Filing date: Jul 28, 2023
• Grant date: May 27, 2025
• Expiry date: Sep 25, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80

Abstract

An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.