System and method for superconducting multi-chip module

US12317757B2 · kind B2 · utility

Assignee

• SeeQC, Inc. · US

Inventors

• Daniel Yohannes · Stamford, US
• Denis Amparo · White Plains, US
• Oleksandr Chernyashevskyy · White Plains, US
• Oleg A. Mukhanov · Putnam Valley, US
• Mario Renzullo · Yonkers, US
• Andrei Talalaeskii · Mahopac, US
• Igor V. Vernik · Yorktown Heights, US
• John Vivalda · Poughkeepsie, US
• Jason Walter · Trumbull, US

Key dates

• Filing date: Jul 24, 2023
• Grant date: May 27, 2025
• Expiry date: Jul 24, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3651
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.