High throughput sort
US12320845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Sep 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems, methods, and circuitry are provided for a sorting array. In one example, a sorting array element includes an output register and control circuitry. The output register is configured to store an output value. In response to a cell under test (CUT) load signal the output register stores a CUT value and in response to a first register shift signal from a previous sorting array element the output register stores contents of an output register of the previous sorting array element. The control circuitry is configured to generate the CUT load signal and a second register shift signal for a subsequent sorting array element based on relative magnitudes of the CUT value, the output value, and an output value stored in the output register of the previous sorting array element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.