Clock control circuit and method
US12320849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2024 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Feb 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure provides a clock control circuit and method for a circuitry. The circuitry includes a scan flip-flop circuit, an at-speed domain and a timing exception domain. The scan flip-flop circuit is configured to output data to the at-speed domain and the timing exception domain. The clock control circuit includes a first gate control circuit, a first gate circuit, a second gate control circuit and a second gate circuit. The first gate circuit is controlled by a first control signal output by the first gate control circuit, a scan enable signal and a scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gate circuit is controlled by a second control signal output by the second gate control circuit to block or output an output signal of the scan flip-flop circuit to the timing exception domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.